*** netboot/tg3.c	Mon Jan  3 01:00:49 2005
--- netboot/tg3.c	Thu Jan  6 19:37:25 2005
***************
*** 8,13 ****
--- 8,14 ----
  
  /* 11-13-2003	timlegge	Fix Issue with NetGear GA302T 
   * 11-18-2003   ebiederm        Generalize NetGear Fix to what the code was supposed to be.
+  * 01-06-2005   Alf (Frederic Olivie) Add Dell bcm 5751 (0x1677) support
   */
  
  #include "etherboot.h"
***************
*** 42,48 ****
  
  /*	(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ? \
  	 512 : 1024) */
!  #define TG3_TX_RING_SIZE		512
  #define TG3_DEF_TX_RING_PENDING		(TG3_TX_RING_SIZE - 1)
  
  #define TG3_RX_RING_BYTES	(sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RING_SIZE)
--- 43,49 ----
  
  /*	(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ? \
  	 512 : 1024) */
! #define TG3_TX_RING_SIZE		512
  #define TG3_DEF_TX_RING_PENDING		(TG3_TX_RING_SIZE - 1)
  
  #define TG3_RX_RING_BYTES	(sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RING_SIZE)
***************
*** 158,163 ****
--- 159,166 ----
  	tp->pci_clock_ctrl = clock_ctrl;
  	
  	if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
+ 	    (!((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+ 	       && (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) &&
  		(orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE)!=0) {
  		tw32_carefully(TG3PCI_CLOCK_CTRL, 
  			clock_ctrl | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
***************
*** 484,489 ****
--- 487,503 ----
  			return err;
  		goto out;
  	}
+ 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ 	  // Taken from Broadcom's source code
+ 	  tg3_writephy(tp, 0x18, 0x0c00);
+ 	  tg3_writephy(tp, 0x17, 0x000a);
+ 	  tg3_writephy(tp, 0x15, 0x310b);
+ 	  tg3_writephy(tp, 0x17, 0x201f);
+ 	  tg3_writephy(tp, 0x15, 0x9506);
+ 	  tg3_writephy(tp, 0x17, 0x401f);
+ 	  tg3_writephy(tp, 0x15, 0x14e2);
+ 	  tg3_writephy(tp, 0x18, 0x0400);
+ 	}
  	err = tg3_bmcr_reset(tp);
  	if (err)
  		return err;
***************
*** 676,682 ****
  	int i, err;
  
  	tw32_carefully(MAC_STATUS,
! 		(MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
  
  	tp->mi_mode = MAC_MI_MODE_BASE;
  	tw32_carefully(MAC_MI_MODE, tp->mi_mode);
--- 690,697 ----
  	int i, err;
  
  	tw32_carefully(MAC_STATUS,
! 		(MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED
! 		 | MAC_STATUS_LNKSTATE_CHANGED));
  
  	tp->mi_mode = MAC_MI_MODE_BASE;
  	tw32_carefully(MAC_MI_MODE, tp->mi_mode);
***************
*** 1534,1543 ****
  	 * REG_WRITE_BUG because we do all register writes indirectly.
  	 */
  
  	/* do the reset */
  	val = GRC_MISC_CFG_CORECLK_RESET;
! 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
  		val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
  	tw32(GRC_MISC_CFG, val);
  
  	/* Flush PCI posted writes.  The normal MMIO registers
--- 1549,1571 ----
  	 * REG_WRITE_BUG because we do all register writes indirectly.
  	 */
  
+ 	// Alf: here patched
  	/* do the reset */
  	val = GRC_MISC_CFG_CORECLK_RESET;
! 	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
! 	    || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
  		val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
+ 	}
+ 
+ 	// Alf : Please VALIDATE THIS.
+ 	// It is necessary in my case (5751) to prevent a reboot, but
+ 	// I have no idea about a side effect on any other version.
+ 	// It appears to be what's done in tigon3.c from Broadcom
+ 	if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
+ 	  tw32(GRC_MISC_CFG, 0x20000000) ;
+ 	  val |= 0x20000000 ;
+ 	}
+ 
  	tw32(GRC_MISC_CFG, val);
  
  	/* Flush PCI posted writes.  The normal MMIO registers
***************
*** 1620,1626 ****
  		return -ENODEV;
  	}
  	if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
! 		state = DRV_STATE_SUSPEND;
  	}
  	tg3_write_mem(NIC_SRAM_FW_DRV_STATE_MBOX, state);
  	return 0;
--- 1648,1661 ----
  		return -ENODEV;
  	}
  	if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
! 	  state = DRV_STATE_SUSPEND;
! 	}
! 
! 	if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
! 	    (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)) {
! 	  // Enable PCIE bug fix
! 	  tg3_read_mem(0x7c00, &val);
! 	  tg3_write_mem(0x7c00, val | 0x02000000);
  	}
  	tg3_write_mem(NIC_SRAM_FW_DRV_STATE_MBOX, state);
  	return 0;
***************
*** 1761,1766 ****
--- 1796,1805 ----
  
  	tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  
+ 	// This should go somewhere else
+ #define T3_PCIE_CAPABILITY_ID_REG           0xD0
+ #define T3_PCIE_CAPABILITY_ID               0x10
+ #define T3_PCIE_CAPABILITY_REG              0xD2
  
  	/* Originally this was all in tg3_reset_hw */
  
***************
*** 1785,1792 ****
  	/* This works around an issue with Athlon chipsets on
  	 * B3 tigon3 silicon.  This bit has no effect on any
  	 * other revision.
  	 */
! 	tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
  	tw32_carefully(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  
  	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
--- 1824,1834 ----
  	/* This works around an issue with Athlon chipsets on
  	 * B3 tigon3 silicon.  This bit has no effect on any
  	 * other revision.
+ 	 * Alf: Except 5750 ! (which reboots)
  	 */
! 
!         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
! 	  tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
  	tw32_carefully(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  
  	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
***************
*** 2178,2184 ****
  	tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
  	tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
  
! 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
  		limit = 8;
  	else
  		limit = 16;
--- 2220,2227 ----
  	tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
  	tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
  
! 	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
! 	    || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750))
  		limit = 8;
  	else
  		limit = 16;
***************
*** 2362,2367 ****
--- 2405,2411 ----
  	{ PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
  	{ PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
  	{ PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
+ 	{ PCI_VENDOR_ID_DELL, 0x0179, PHY_ID_BCM5751 }, /* EtherXpress */
  
  	/* Compaq boards. */
  	{ PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
***************
*** 2623,2628 ****
--- 2667,2673 ----
  	uint32_t pci_state_reg, grc_misc_cfg;
  	uint16_t pci_cmd;
  	uint8_t  pci_latency;
+ 	uint32_t val ;
  	int err;
  
  	/* Read the subsystem vendor and device ids */
***************
*** 2708,2713 ****
--- 2753,2771 ----
  		pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
  	}
  
+ 	/* determine if it is PCIE system */
+ 	// Alf : I have no idea what this is about...
+ 	// But it's definitely usefull
+ 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ 	  val = tr32(TG3PCI_MSI_CAP_ID) ;
+ 	  if (((val >> 8) & 0xff) == T3_PCIE_CAPABILITY_ID_REG) {
+ 	    val = tr32(T3_PCIE_CAPABILITY_ID_REG) ;
+ 	    if ((val & 0xff) == T3_PCIE_CAPABILITY_ID) {
+ 	      tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS ;
+ 	    }
+ 	  }
+ 	}
+ 
  	/* Force the chip into D0. */
  	tg3_set_power_state_0(tp);
  
***************
*** 2717,2722 ****
--- 2775,2781 ----
  
  	/* A few boards don't want Ethernet@WireSpeed phy feature */
  	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
+ 	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
  		((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  			(tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
  			(tp->pci_chip_rev_id != CHIPREV_ID_5705_A1))) {
***************
*** 2906,2911 ****
--- 2965,2976 ----
  		tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
  	}
  
+ 	/*
+ 	  Alf : Tried that, but it does not work. Should be this way though :-(
+ 	if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
+     	  tp->dma_rwctrl |= 0x001f0000;
+ 	}
+ 	*/
  	tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
  
  	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
***************
*** 3298,3303 ****
--- 3363,3369 ----
  PCI_ROM(0x14e4, 0x1654, "tg3-5705_2",      "Broadcom Tigon 3 5705_2"),
  PCI_ROM(0x14e4, 0x165d, "tg3-5705M",       "Broadcom Tigon 3 5705M"),
  PCI_ROM(0x14e4, 0x165e, "tg3-5705M_2",     "Broadcom Tigon 3 5705M_2"),
+ PCI_ROM(0x14e4, 0x1677, "tg3-5751",        "Broadcom Tigon 3 5751"),
  PCI_ROM(0x14e4, 0x1696, "tg3-5782",        "Broadcom Tigon 3 5782"),
  PCI_ROM(0x14e4, 0x169c, "tg3-5788",        "Broadcom Tigon 3 5788"),
  PCI_ROM(0x14e4, 0x16a6, "tg3-5702X",       "Broadcom Tigon 3 5702X"),
*** netboot/tg3.h	Sun Dec  7 16:11:42 2003
--- netboot/tg3.h	Thu Jan  6 12:53:44 2005
***************
*** 283,294 ****
--- 283,298 ----
  #define  CHIPREV_ID_5705_A1		 0x3001
  #define	 CHIPREV_ID_5705_A2              0x3002
  #define  CHIPREV_ID_5705_A3              0x3003
+ #define  CHIPREV_ID_5750_A0              0x4000
+ #define  CHIPREV_ID_5750_A1              0x4001
+ #define  CHIPREV_ID_5750_A3              0x4003
  #define  GET_ASIC_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 12)
  #define   ASIC_REV_5700			 0x07
  #define   ASIC_REV_5701			 0x00
  #define   ASIC_REV_5703			 0x01
  #define   ASIC_REV_5704			 0x02
  #define   ASIC_REV_5705			 0x03
+ #define   ASIC_REV_5750			 0x04
  #define  GET_CHIP_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 8)
  #define   CHIPREV_5700_AX		 0x70
  #define   CHIPREV_5700_BX		 0x71
***************
*** 2064,2069 ****
--- 2068,2075 ----
  #define TG3_FLG2_IS_5788		0x00000008
  #define TG3_FLG2_MAX_RXPEND_64		0x00000010
  #define TG3_FLG2_TSO_CAPABLE		0x00000020
+   // Alf: Hope I'm not breaking anything here !
+ #define TG3_FLG2_PCI_EXPRESS            0x00000040
  
  
  
***************
*** 2124,2129 ****
--- 2130,2136 ----
  #define PHY_ID_BCM5704			0x60008190
  #define PHY_ID_BCM5705			0x600081a0
  #define PHY_ID_BCM8002			0x60010140
+ #define PHY_ID_BCM5751			0x00206180
  #define PHY_ID_SERDES			0xfeedbee0
  #define PHY_ID_INVALID			0xffffffff
  #define PHY_ID_REV_MASK			0x0000000f
***************
*** 2148,2154 ****
  	((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
  	 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
  	 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
! 	 (X) == PHY_ID_BCM5705 || \
  	 (X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES)
  
  	unsigned long			regs;
--- 2155,2161 ----
  	((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
  	 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
  	 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
! 	 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5751 || \
  	 (X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES)
  
  	unsigned long			regs;
